Known memory devices include dynamic random access memory (DRAM), static random access memory (SRAM) and pseudo-static random access memory (PSRAM). In general, a DRAM includes at least one array of memory cells. The memory cells in the array of memory cells are arranged in rows and columns. Conductive word lines extend across the array of memory cells along the row direction and conductive bit lines extend across the array of memory cells along the column direction. A memory cell is located at each cross point of a word line and a bit line or a bit line pair. Memory cells are accessed using a row address and a column address.
DRAM memory cells are essentially made up of a capacitor, and data are stored in the DRAM memory cells in the form of electric charges that need to be periodically refreshed. SRAM memory cells store data using flip-flops, so an SRAM has faster access time as compared to a DRAM, and refreshing memory cells is not required with an SRAM. However, an SRAM generally is larger in size and consumes more power than a DRAM.
A PSRAM is a DRAM that operates according to an SRAM standard. In other words, the refresh operation required for the DRAM is hidden from the device using the memory. PSRAMs are used, for example, in wireless applications where small size and low power use is desirable. Time for refresh operations can be provided by allowing time for a refresh with each memory access. While such a refresh scheme provides a fixed latency solution, compared to the normal row cycle time of an actively operated PSRAM, refreshes occur rarely. For example, time between refreshes is typically about 7.8 μs, with a typical cycle time of 100 ns. This results in about 78 memory accesses without a refresh for each access with a refresh, unnecessarily slowing performance of the device. In other prior art attempted solutions, time for refresh is only provided with a memory access when a refresh is necessary. This results in variable latency, or varying access times, since the memory access time is increased each time a refresh is required as compared to a memory access without a refresh.